1. Field of the Invention
The present invention relates to the field of power management. More specifically, the present invention relates to power management in computer systems.
2. Description of Related Art
With the advent of mobile computers and mobile computer systems it has become increasingly important to minimize power consumed by these devices or systems. One major consumer of power, in mobile computer systems, is the central processing unit (CPU). Microprocessors, consume appreciable amounts of power, each time a dock pulse occurs. Existing power management systems have focused their attention on reducing the power consumed by the CPU. As it is well known, the amount of power consumed by the CPU is proportional to the frequency of the clock sequencing the operation of the CPU. Because CPUs spend a large percentage of time in idle loops, waiting for input-output operations to complete, waiting for operator input, etc., most power management systems have concentrated on reducing CPU clock speed during periods of CPU inactivity and during periods wherein the operations performed by the CPU do not require high dock frequencies.
A significant amount of power, however, is consumed by other parts of the computer, besides the CPU. For example, the chipset or host Peripheral Component Interconnect (PCI) bridge is a significant consumer of power. Some parts of the chipset which consume substantial amounts of power, however, are not required to be functional during certain periods of time. For example, a dynamic random access memory (DRAM) controller, which is a circuit in the chipset responsible for controlling the exchange of information between a DRAM and a host CPU or between the DRAM and other external circuits such as a PCI bus, may not be required to operate at full speed or at all when the CPU or the PCI bus are not exchanging information with the DRAM. PCI bus architecture is explained in detail in the PCI Local Bus Specification, Revision 2.1 of the PCI Special Interest Group of Portland, Oreg.
FIG. 1 shows a computer system including a host CPU 2 having a bus controller 4 responsible for the exchange of information between the host CPU 2 and other devices connected to a local bus 6. A chipset 10 is coupled to the host CPU 2 and to the local bus 6. The chipset 10 includes a memory controller 8 which controls the exchange of information between the CPU2 and a memory 12. Memory 12, by way of example, could be a DRAM memory while memory controller 8 can be a DRAM controller.
In the event the CPU is not exchanging information with the chipset 10, via bus controller 4, no activity will take place between the bus controller 4 and the memory controller 8 of chipset 10. In this case, assuming that other devices which might be coupled to the memory controller 8, such as a PCI bus controller (not shown), are not accessing memory controller 8, it is desirable to reduce the power consumed by the idle memory controller 8. One way to reduce the power consumed by memory controller 8 would be to shut off the dock which provides periodical pulses to the memory controller 8. Since the power dissipated by a device sequenced by a dock having the frequency F, is proportional to F according to the formula, EQU P=CV.sup.2 F
where V is the voltage supplied to the memory controller, and C is the capacitance of the memory controller, the power dissipated would thus be substantially reduced if the frequency of the dock approached 0 Herz.
Current practices use dock gating techniques for shutting off the dock to a device. Such techniques, however, do not offer an intelligent way to shut off the clock of a device such as the memory controller of FIG. 1, because they do not take into account the fact that the memory controller, after having been shut off, may need to restart operation promptly upon the occurrence of a certain event. For example, if the bus controller 4 of FIG. 1, resumes activity due to the receipt of a bus request signal from a CPU core, (not shown in FIG. 1) the memory controller should timely resume activity to service a new DRAM access. In this case, conventional dock gating techniques do not offer an adequate mechanism for powering back the memory controller at the right time without wasting bus cycles.
It is thus desirable to provide an apparatus and a method for detecting events wherein power monitoring devices, which control a power dissipating device, can timely identify an event which requires the power controlled device to timely switch into a fully operational mode. More specifically, it is desirable to provide an apparatus and method according to which the power dissipated by a memory controller or any other devices coupled to the host bus, is regulated in instances where the CPU's bus controller and the PCI bus controller are idle. Additionally, it is desirable to provide for a method and apparatus for restoring the operation of the memory controller in coordination with the beginning of activity of the bus controller such that no bus cycles are wasted when the bus controller has become active. It is also desirable to provide the foregoing advantages to a computer system having other external devices coupled to the chipset such as a PCI bus, so that a portion of the chipset can be power controlled when both the CPU (master) and the external devices (slave) are not using a certain portion of the chipset coupled to both the master and the slave.